Debug and trace tools and techniques play an exceptionally important role at all stages of design of integrated circuitry. Debugging complex Systems on a Chip (SoC) requires the observability of internal signals at speed. This needs to be possible without any influence on the real time behavior of the SoC.
Modern telecommunications modems require complex Systems-on-Chip (SoC) solutions and they are very hard to debug if the system does not provide dedicated debug and trace capabilities. Typically, a modem is implemented using one or more processor cores that control additional computational logic.
Debugging typically refers to the detection and resolution of behavioral flaws of the software running on the embedded cores. For debugging, special test modes are implemented in the SoC.
Traditional debug and software based tracing techniques can be often unacceptably invasive, burdensome or impractical. Current hardware assisted tracing techniques help, but there are still many limitations. Also, a system wide approach is necessary to analyze the interoperations between the many processing agents and the complex infrastructure on an SoC. When debugging the embedded software, the SoC is most likely not working at speed, and parts of the SoC are isolated for better controllability and observability (measure for how well internal states of a system can be inferred by knowledge of its external outputs). Controllability and observability are dual aspects of the same problem.
In order to assist the implementer with identifying programming or implementation flaws on a system level, modern implementations include several trace features.
Trace features allow observability of internal signals in a normal operation mode whereas the normal function is not influenced by the trace.
One example of a conventional trace architecture is ARM's CoreSight® architecture, see e.g. at http://wvvw.arm.com/products/system-ip/debug-trace/coresight-architecture.php. In a typical System-on-Chip implementation, the CoreSight® infrastructure includes a debug subsystem and a trace subsystem. Each processing element (DSP, CPU etc.) can be paired with an instruction/data trace IP block (ETM—Embedded Trace Module) or program (PTM) trace IP block, enabling it to generate trace information about executed instructions or program flow respectively. This architecture, however, requires much additional logic such as a trace arbiter and ETMs, many multiplexers, additional large buses and large wiring overhead. So the main disadvantage of this approach is the additional hardware cost of the additional trace circuitry.
In summary, a deficiency of the prior art is that both test and trace features need additional dedicated hardware resources which are consuming extra power and increase the cost by increasing the die size of a chip, while the challenge remains that the system behavior must not be influenced by real time tracing.